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intel386? ex embedded microprocessor datasheet product features this datasheet applies to devices marked extb and extc. if you require information about devices marked exsa or exta, refer to a previous revision of this datasheet, order number 272420-004. n static intel386? cpu core low power consumption operating power supply extb: 2.7 v to 3.6 v extc: 4.5 v to 5.5 v operating frequency 20 mhz extb at 2.7 v to 3.6 v 25 mhz extb at 3.0 v to 3.6 v; 25/33 mhz extc at 4.5 v to 5.5 v n transparent power-management system architecture intel system management mode architecture extension for truly compatible systems power management transparent to operating systems and application programs programmable power-management modes n powerdown mode clock stopping at any time only 10C20 a typical cpu sink current n full 32-bit internal architecture 8-, 16-, 32-bit data types 8 general purpose 32-bit registers n runs intel386 architecture software in a cost-effective 16-bit hardware environment runs same applications and operating systems as the intel386 sx and intel386 dx processors object code compatible with 8086, 80186, 80286, and intel386 processors n high-performance 16-bit data bus two-clock bus cycles address pipelining allows use of slower, inexpensive memories n extended temperature range n integrated memory management unit virtual memory support optional on-chip paging 4 levels of hardware-enforced protection mmu fully compatible with mmus of the 80286 and intel386 dx processors n virtual 8086 mode allows execution of 8086 software in a protected and paged system n large uniform address space 64 megabyte physical 64 terabyte virtual 4 gigabyte maximum segment size n on-chip debugging support including breakpoint registers n complete system development support n high speed chmos technology n two package types 132-pin plastic quad flatpack 144-pin thin quad flatpack n integrated peripheral functions clock and power management unit chip-select unit interrupt control unit timer/counter unit watchdog timer unit asynchronous serial i/o unit synchronous serial i/o unit parallel i/o unit dma and bus arbiter unit refresh control unit jtag-compliant test-logic unit order number: 272420-007 october 1998
datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel386? ex microprocessor may contain design defects or errors known as errata which may cause the product to deviate fro m published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1998 *third-party brands and names are the property of their respective owners.
datasheet 3 intel386? ex embedded microprocessor contents 1.0 introduction ..................................................................................................................7 2.0 pin assignment ...........................................................................................................8 3.0 pin description ..........................................................................................................12 4.0 functional description ...........................................................................................19 4.1 clock generation and power management unit ................................................. 19 4.2 chip-select unit ...................................................................................................19 4.3 interrupt control unit ...........................................................................................19 4.4 timer/counter unit .............................................................................................. 20 4.5 watchdog timer unit........................................................................................... 20 4.6 asynchronous serial i/o unit ..............................................................................20 4.7 synchronous serial i/o unit ................................................................................ 21 4.8 parallel i/o unit ...................................................................................................21 4.9 dma and bus arbiter unit ...................................................................................21 4.10 refresh control unit............................................................................................22 4.11 jtag test-logic unit ...........................................................................................22 5.0 design considerations ..........................................................................................23 5.1 instruction set .....................................................................................................23 5.2 component and revision identifiers ................................................................... 24 5.3 package thermal specifications .........................................................................24 6.0 electrical specifications ........................................................................................27 6.1 maximum ratings................................................................................................27 6.2 dc specifications ................................................................................................28 6.3 ac specifications ................................................................................................30 7.0 bus cycle waveforms ............................................................................................47 figures 1 intel386? ex embedded processor block diagram ............................................ 7 2 intel386? ex embedded processor 132-pin pqfp pin assignment .................. 8 3 intel386? ex embedded processor 144-pin tqfp pin assignment................. 10 4 maximum case temperature vs. frequency for typical power values (132-lead pqfp, v cc = 5.5 v) .............................................................................25 5 maximum case temperature vs. frequency for typical power values (144-lead tqfp, v cc = 5.5 v nominal) ................................................................25 6 maximum case temperature vs. frequency for typical power values (132-lead pqfp, v cc = 3.6 v) .............................................................................26 7 maximum case temperature vs. frequency for typical power values (144-lead tqfp, v cc = 3.6 v)..............................................................................26 8 drive levels and measurement points for ac specifications (extc) ................ 30 9 drive levels and measurement points for ac specifications (extb) ................ 31 10 ac test loads..................................................................................................... 42
intel386? ex embedded microprocessor 4 datasheet 11 clk2 waveform .................................................................................................. 42 12 ac timing waveforms input setup and hold timing ..................................... 43 13 ac timing waveforms output valid delay timing ......................................... 44 14 ac timing waveforms output valid delay timing for external late ready#........................................................................................ 44 15 ac timing waveforms output float delay and hlda valid delay timing .... 45 16 ac timing waveforms reset setup and hold timing and internal phase .. 45 17 ac timing waveforms relative signal timing ............................................... 46 18 ac timing waveforms ssio timing .............................................................. 46 19 ac timing waveforms timer/counter timing ................................................ 46 20 basic internal and external bus cycles .............................................................. 47 21 nonpipelined address read cycles.................................................................... 48 22 pipelined address cycle ..................................................................................... 49 23 16-bit cycles to 8-bit devices (using bs8#) ........................................................50 24 basic external bus cycles ..................................................................................51 25 nonpipelined address write cycles .................................................................... 52 26 halt cycle ............................................................................................................53 27 basic refresh cycle ............................................................................................ 54 28 refresh cycle during hold/hlda ....................................................................55 29 lock# signal during address pipelining ........................................................... 56 30 interrupt acknowledge cycles............................................................................. 56 tables 1 132-pin pqfp pin assignment ............................................................................. 9 2 144-pin tqfp pin assignment ........................................................................... 11 3 pin type and output state nomenclature .......................................................... 12 4 intel386? ex microprocessor pin descriptions .................................................13 5 microprocessor clocks per instruction................................................................ 23 6 thermal resistances (0c/w) q ja , q jc ................................................................ 24 7 5 v intel386 extc processor maximum ratings ............................................... 27 8 3 v intel386 extb processor maximum ratings................................................ 27 9 5-volt dc characteristics.................................................................................... 28 10 3-volt dc characteristics.................................................................................... 29 11 5-volt ac characteristics .................................................................................... 32 12 3-volt ac characteristics .................................................................................... 37
datasheet 5 intel386? ex embedded microprocessor revision history this datasheet applies to devices marked extb and extc. if you require information about devices marked exsa or exta, refer to a previous revision of this datasheet, order number 272420-004. revision date description 007 10/98 the document was updated to the larger page size. all known device errata for the datasheet have been incorporated into this new revision. 006 5/96 corrections added. 005 12/95 this datasheet applied to the new extb and extc devices. 004 9/94 this datasheet applied to devices marked exsa or exta.

intel386? ex embedded microprocessor datasheet 7 1.0 introduction the intel386? extb embedded processor operates at 20 or 25 mhz at 3 volts nominal. the intel386 extc embedded processor operates at 25 or 33 mhz at 5 volts. in this datasheet, intel386 ex processor refers to both the intel386 extb and extc processors. the intel386 ex embedded processor is a highly integrated, 32-bit, fully static processor optimized for embedded control applications. with a 16-bit external data bus, a 26-bit external address bus, and intels system management mode (smm), the intel386 ex microprocessor brings the vast software library of intel386 architecture to embedded systems. it provides the performance benefits of 32-bit programming with the cost savings associated with 16-bit hardware systems. figure 1. intel386? ex embedded processor block diagram a2849-02 jtag unit clock and power management unit dram refresh control unit watchdog timer unit bus monitor asynchronous serial i/o 2 channels (16450 compatible) synchronous serial i/o 1 channel, full duplex timer/counter unit 3 channels (82c54 compatible) i/o ports data address bus interface unit intel386 ? cx core core enhancements - a20 gate - cpu reset - smm chip-select unit interrupt control unit dma controller 2 channels (8237a compatible) and bus arbiter unit intr address data processor core
intel386? ex embedded microprocessor 8 datasheet 2.0 pin assignment figure 2. intel386? ex embedded processor 132-pin pqfp pin assignment note: nc = no connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 flt# dsr1#/stxclk vss int7/tmrgate1 int6/tmrclk1 int5/tmrgate0 int4/tmrclk0 busy#/tmrgate2 error#/tmrout2 nmi pereq/tmrclk2 vcc p3.7/comclk p3.6/pwrdown p3.5/int3 p3.4/int2 vss p3.3/int1 vcc p3.2/int0 rts1#/ssiotx ri1#/ssiorx dtr1#/srxclk tck p3.1/tmrout1/int8 p3.0/tmrout0/int9 smi# a25 vcc a24 vss a23 a22 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 ucs# cs6#/refresh# vss lba# d0 d1 d2 d3 vcc d4 d5 d6 d7 d8 vcc d9 vss d10 d11 d12 d13 d14 d15 tdo tdi tms m/io# vcc d/c# w/r# vss ready# bs8# p2.7/cts0# p2.6/txd0 vss p2.5/rxd0 dack0#/cs5# vcc p2.4/cs4# p2.3/cs3# p2.2/cs2# p2.1/cs1# p2.0/cs0# vcc smiact# trst# drq1/rxd1 drq0/dcd1# vss clk2 wdtout eop#/cts1# dack1#/txd1 p1.7/hlda reset vcc p1.6/hold p1.5/lock# p1.4/ri0# p1.3/dsr0# p1.2/dtr0# clkout p1.1/rts0# p1.0/dcd0# vss rd# wr# vss ble# vcc bhe# ads# na# a1 a2 a3 a4 vss vcc a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16/cas0 vcc a17/cas1 a18/cas2 a19 vss a20 a21 top view a2212-02
intel386? ex embedded microprocessor datasheet 9 table 1. 132-pin pqfp pin assignment pin symbol pin symbol pin symbol pin symbol 1 ucs# 34 rd# 67 a22 100 v ss 2 cs6#/refresh# 35 wr# 68 a23 101 p1.0/dcd0# 3v ss 36 v ss 69 v ss 102 p1.1/rts0# 4 lba# 37 ble# 70 a24 103 clkout 5d0 38v cc 71 v cc 104 p1.2/dtr0# 6 d1 39bhe# 72a25 105p1.3/dsr0# 7 d2 40ads# 73smi# 106p1.4/ri0# 8 d3 41 na# 74 p3.0/tmrout0/int9 107 p1.5/lock# 9v cc 42 a1 75 p3.1/tmrout1/int8 108 p1.6/hold 10 d4 43 a2 76 tck 109 v cc 11 d5 44 a3 77 dtr1#/srxclk 110 reset 12 d6 45 a4 78 ri1#/ssiorx 111 p1.7/hlda 13 d7 46 v ss 79 rts1#/ssiotx 112 dack1#/txd1 14 d8 47 v cc 80 p3.2/int0 113 eop#/cts1# 15 v cc 48 a5 81 v cc 114 wdtout 16 d9 49 a6 82 p3.3/int1 115 clk2 17 v ss 50 a7 83 v ss 116 v ss 18 d10 51 a8 84 p3.4/int2 117 drq0/dcd1# 19 d11 52 a9 85 p3.5/int3 118 drq1/rxd1 20 d12 53 a10 86 p3.6/pwrdown 119 trst# 21 d13 54 a11 87 p3.7/comclk 120 smiact# 22 d14 55 a12 88 v cc 121 v cc 23 d15 56 a13 89 pereq/tmrclk2 122 p2.0/cs0# 24 tdo 57 a14 90 nmi 123 p2.1/cs1# 25 tdi 58 a15 91 error#/tmrout2 124 p2.2/cs2# 26 tms 59 a16/cas0 92 busy#/tmrgate2 125 p2.3/cs3# 27 m/io# 60 v cc 93 int4/tmrclk0 126 p2.4/cs4# 28 v cc 61 a17/cas1 94 int5/tmrgate0 127 v cc 29 d/c# 62 a18/cas2 95 int6/tmrclk1 128 dack0#/cs5# 30 w/r# 63 a19 96 int7/tmrgate1 129 p2.5/rxd0 31 v ss 64 v ss 97 v ss 130 v ss 32 ready# 65 a20 98 dsr1#/stxclk 131 p2.6/txd0 33 bs8# 66 a21 99 flt# 132 p2.7/cts0#
intel386? ex embedded microprocessor 10 datasheet figure 3. intel386? ex embedded processor 144-pin tqfp pin assignment vss flt# dsr1#/stxclk vss int7/tmrgate1 int6/tmrclk1 int5/tmrgate0 int4/tmrclk0 busy#/tmrgate2 error#/tmrout2 nmi vss pereq/tmrclk2 vcc p3.7/comclk p3.6/pwrdown p3.5/int3 p3.4/int2 vss p3.3/int1 vcc p3.2/int0 rts1#/ssiotx ri1#/ssiorx dtr1#/srxclk vss tck p3.1/tmrout1/int8 p3.0/tmrout0/int9 smi# a25 vcc a24 vss a23 a22 rd# wr# vss ble# vcc bhe# ads# na# a1 a2 vss a3 a4 vss vcc a5 a6 a7 a8 a9 a10 a11 a12 vss a13 a14 a15 a16/cas0 vcc a17/cas1 a18/cas2 a19 vss a20 a21 vss vss p2.7/cts0# p2.6/txd0 vss p2.5/rxd0 dack0#/cs5# vcc p2.4/cs4# p2.3/cs3# p2.2/cs2# p2.1/cs1# p2.0/cs0# vss vcc smiact# trst# drq1/rxd1 drq0/dcd1# vss clk2 wdtout eop#/cts1# dack1#/txd1 p1.7/hlda vss reset vcc p1.6/hold p1.5/lock# p1.4/ri0# p1.3/dsr0# p1.2/dtr0# clkout p1.1/rts0# p1.0/dcd0# vss ucs# cs6#/refresh# vss lba# d0 d1 d2 d3 vcc d4 vss d5 d6 d7 d8 vcc d9 vss d10 d11 d12 d13 d14 vss d15 tdo tdi tms m/io# vcc d/c# w/r# vss ready# bs8# vss top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 a2213-03
intel386? ex embedded microprocessor datasheet 11 table 2. 144-pin tqfp pin assignment pin symbol pin symbol pin symbol pin symbol 1 ucs# 37 rd# 73 a22 109 v ss 2 cs6#/refresh# 38 wr# 74 a23 110 p1.0/dcd0# 3v ss 39 v ss 75 v ss 111 p1.1/rts0# 4 lba# 40 ble# 76 a24 112 clkout 5d0 41v cc 77 v cc 113 p1.2/dtr0# 6 d1 42 bhe# 78 a25 114 p1.3/dsr0# 7 d2 43 ads# 79 smi# 115 p1.4/ri0# 8 d3 44 na# 80 p3.0/tmrout0/int9 116 p1.5/lock# 9v cc 45 a1 81 p3.1/tmrout1/int8 117 p1.6/hold 10 d4 46 a2 82 tck 118 v cc 11 v ss 47 v ss 83 v ss 119 reset 12 d5 48 a3 84 dtr1#/srxclk 120 v ss 13 d6 49 a4 85 ri1#/ssiorx 121 p1.7/hlda 14 d7 50 v ss 86 rts1#/ssiotx 122 dack1#/txd1 15 d8 51 v cc 87 p3.2/int0 123 eop#/cts1# 16 v cc 52 a5 88 v cc 124 wdtout 17 d9 53 a6 89 p3.3/int1 125 clk2 18 v ss 54 a7 90 v ss 126 v ss 19 d10 55 a8 91 p3.4/int2 127 drq0/dcd1# 20 d11 56 a9 92 p3.5/int3 128 drq1/rxd1 21 d12 57 a10 93 p3.6/pwrdown 129 trst# 22 d13 58 a11 94 p3.7/comclk 130 smiact# 23 d14 59 a12 95 v cc 131 v cc 24 v ss 60 v ss 96 pereq/tmrclk2 132 v ss 25 d15 61 a13 97 v ss 133 p2.0/cs0# 26 tdo 62 a14 98 nmi 134 p2.1/cs1# 27 tdi 63 a15 99 error#/tmrout2 135 p2.2/cs2# 28 tms 64 a16/cas0 100 busy#/tmrgate2 136 p2.3/cs3# 29 m/io# 65 v cc 101 int4/tmrclk0 137 p2.4/cs4# 30 v cc 66 a17/cas1 102 int5/tmrgate0 138 v cc 31 d/c# 67 a18/cas2 103 int6/tmrclk1 139 dack0#/cs5# 32 w/r# 68 a19 104 int7/tmrgate1 140 p2.5/rxd0 33 v ss 69 v ss 105 v ss 141 v ss 34 ready# 70 a20 106 dsr1#/stxclk 142 p2.6/txd0 35 bs8# 71 a21 107 flt# 143 p2.7/cts0# 36 v ss 72 v ss 108 v ss 144 v ss
intel386? ex embedded microprocessor 12 datasheet 3.0 pin description table 4 lists the intel386 ex embedded processor pin descriptions. table 3 defines the abbreviations used in the type and output states columns of table 4. table 3. pin type and output state nomenclature symbol description pin type # i o i/o i/od st p g the named signal is active low. standard ttl input signal. standard cmos output signal. input and output signal. input and open-drain output signal. schmitt-triggered input signal. power pin. ground pin. output state h(1) h(0) h(z) h(q) h(x) output driven to v cc during bus hold output driven to v ss during bus hold output floats during bus hold output remains active during bus hold output retains current state during bus hold r(wh) r(wl) r(1) r(0) r(z) r(q) r(x) output weakly held at v cc during reset output weakly held at v ss during reset output driven to v cc during reset output driven to v ss during reset output floats during reset output remains active during reset output retains current state during reset i(1) ? i(0) i(z) i(q) i(x) output driven to v cc during idle mode output driven to v ss during idle mode output floats during idle mode output remains active during idle mode output retains current state during idle mode p(1) p(0) p(z) p(q) p(x) output driven to v cc during powerdown mode output driven to v ss during powerdown mode output floats during powerdown mode output remains active during powerdown mode output retains current state during powerdown mode ? the idle mode output states assume that no internal bus master (dma or rcu) has control of the bus during idle mode
intel386? ex embedded microprocessor datasheet 13 ta ble 4 . intel386? ex microprocessor pin descriptions (sheet 1 of 6) symbol type output states name and function a25:1 o h(z) r(1) i(1) p(1) address bus outputs physical memory or port i/o addresses. these signals are valid when ads# is active and remain valid until the next t1, t2p, or ti. during hold cycles they are driven to a high-impedance state. a18:16 are multiplexed with cas2:0. ads# o h(z) r(1) i(1) p(1) address status indicates that the processor is driving a valid bus-cycle definition and address (w/r#, d/c#, m/io#, a25:1, bhe#, ble#) onto its pins. bhe# o h(z) r(0) i(x) p(0) byte high enable indicates that the processor is transferring a high data byte. ble# o h(z) r(0) i(x) p(1) byte low enable indicates that the processor is transferring a low data byte. bs8# i bus size indicates that an 8-bit device is currently being addressed. busy# i busy indicates that the math coprocessor is busy. if busy# is sampled low at the falling edge of reset, the processor performs an internal self test. busy# is multiplexed with tmrgate2 and has a temporary weak pull-up resistor. cas2:0 o h(z) r(1) i(1) p(1) cascade address carries the slave address information from the 8259a master interrupt module during interrupt acknowledge bus cycles. cas2:0 are multiplexed with a18:16. clk2 st clock input is connected to an external clock that provides the fundamental timing for the device. clkout o h(q) r(q) i(q) p(0) clkout is a ph1p clock output. comclk i serial communications baud clock is an alternate clock source for the asynchronous serial ports. comclk is multiplexed with p3.7 and has a temporary weak pull-down resistor. cs4:0# o h(1) r(wh) i(q) p(x) chip-selects are activated when the address of a memory or i/o bus cycle is within the address region programmed by the user. they are multiplexed as follows: cs6# with refresh#, cs5# with dack0#, and cs4:0# with p2.4:0. cs6:5# o h(1) r(1) i(q) p(x) chip-selects are activated when the address of a memory or i/o bus cycle is within the address region programmed by the user. they are multiplexed as follows: cs6# with refresh#, cs5# with dack0#, and cs4:0# with p2.4:0. cts1:0# i clear to send sio1 and sio0 prevent the transmission of data to the asynchronous serial ports rxd1 and rxd0 pins, respectively. cts1# is multiplexed with eop#, and cts0# is multiplexed with p2.7. cts1# requires an external pull-up resistor. both have temporary weak pull-up resistors. notes: 1. x if clock source is internal; q if clock source is external 2. q if jtag unit is shifting out data, z if it is not
intel386? ex embedded microprocessor 14 datasheet d15:0 i/o h(z) r(z) p(z) data bus inputs data during memory read, i/o read, and interrupt acknowledge cycles and outputs data during memory and i/o write cycles. during writes, this bus is driven during phase 2 of t1 and remains active until phase 2 of the next t1, t1p, or ti. during reads, data is latched on the falling edge of phase 2. dack1:0# o h(1) r(1) i(q) p(x) dma acknowledge 1 and 0 signal to an external device that the processor has acknowledged the corresponding dma request and is relinquishing the bus. dack1# is multiplexed with txd1, and dack0# is multiplexed with cs5#. d/c# o h(z) r(1) i(0) p(0) data/control indicates whether the current bus cycle is a data cycle (memory or i/o read or write) or a control cycle (interrupt acknowledge, halt, or code fetch). dcd1:0 i data carrier detect sio1 and sio0 indicate that the modem or data set has detected the corresponding asynchronous serial channels data carrier. dcd1# is multiplexed with drq0, and dcd0# is multiplexed with p1.0 and has a temporary weak pull- up resistor. drq1:0 i dma external request 1 and 0 indicate that a peripheral requires dma service. drq1 is multiplexed with rxd1, and drq0 is multiplexed with dcd1#. dsr1:0# i data set ready sio1 and sio0 indicate that the modem or data set is ready to establish a communication link with the corresponding asynchronous serial channel. dsr1# is multiplexed with stxclk and has a permanent weak pull-up resistor, and dsr0# is multiplexed with p1.3 and has a temporary weak pull-up resistor. dtr1:0# o h(x) r(wh) i(x) p(x) data terminal ready sio1 and sio0 indicate that the corresponding asynchronous serial channel is ready to establish a communication link with the modem or data set. dtr1# is multiplexed with srxclk, and dtr0# is multiplexed with p1.2. eop# i/od h(z) r(wh) i(z) p(z) end of process indicates that the processor has reached terminal count during a dma transfer. an external device can also pull this pin low. eop# is multiplexed with cts1#. error# i error indicates that the math coprocessor has an error condition. error# is multiplexed with tmrout2 and has a temporary weak pull-up resistor. flt# i float forces all bidirectional and output signals except tdo to a high-impedance state. it has a permanent weak pull-up resistor. this pin should be tied to v cc through a 3 to 7 kohm pull-up resistor. hlda o h(1) r(wl) i(q) p(x) bus hold acknowledge indicates that the processor has surrendered control of its local bus to another bus master. hlda is multiplexed with p1.7. hold i bus hold request allows another bus master to request control of the local bus. hlda active indicates that bus control has been granted. hold is multiplexed with p1.6. it has a temporary weak pull-down resistor. table 4. intel386? ex microprocessor pin descriptions (sheet 2 of 6) symbol type output states name and function notes: 1. x if clock source is internal; q if clock source is external 2. q if jtag unit is shifting out data, z if it is not
intel386? ex embedded microprocessor datasheet 15 int9:0 i interrupt requests are maskable inputs that cause the cpu to suspend execution of the current program and then execute an interrupt acknowledge cycle. they are multiplexed as follows: int9 with tmrout0 and p3.0, int8 with tmrout1 and p3.1, int7 with tmrgate1, int6 with tmrclk1, int5 with tmrgate0, int4 with tmrclk0, and int3:0 with p3.5:2. int9, int8, and int3:0 have temporary weak pull-down resistors. lba# o h(1) r(1) i(q) p(x) local bus access is asserted whenever the processor provides the ready# signal to terminate a bus transaction. this occurs when an internal peripheral address is accessed or when the chip-select unit provides the ready# signal. lock# o h(z) r(wh) i(x) p(x) bus lock prevents other bus masters from gaining control of the system bus. lock# is multiplexed with p1.5. m/io# o h(z) r(0) i(1) p(1) memory/io indicates whether the current bus cycle is a memory cycle or an i/o cycle. when m/io# is high, the bus cycle is a memory cycle; when m/io# is low, the bus cycle is an i/o cycle. na# i next address requests address pipelining. nmi st nonmaskable interrupt request is a non-maskable input that causes the cpu to suspend execution of the current program and execute an interrupt acknowledge cycle. pereq i processor extension request indicates that the math coprocessor has data to transfer to the processor. pereq is multiplexed with tmrclk2 and has a temporary weak pull-down resistor. p1.5:0 i/o h(x) r(wh) i(x) p(x) port 1, pins 7:0 are multipurpose bidirectional port pins. they are multiplexed as follows: p1.7 with hlda, p1.6 with hold, p1.5 with lock#, p1.4 with ri0#, p1.3 with dsr0#, p1.2 with dtr0#, p1.1 with rts0#, and p1.0 with dcd0#. p1.7:6 i/o h(x) r(wl) i(x) p(x) port 1, pins 7:0 are multipurpose bidirectional port pins. they are multiplexed as follows: p1.7 with hlda, p1.6 with hold, p1.5 with lock#, p1.4 with ri0#, p1.3 with dsr0#, p1.2 with dtr0#, p1.1 with rts0#, and p1.0 with dcd0#. p2.7,4:0 i/o h(x) r(wh) i(x) p(x) port 2, pins 7:0 are multipurpose bidirectional port pins. they are multiplexed as follows: p2.7 with cts0#, p2.6 with txd0, p2.5 with rxd0, and p2.4:0 with cs4:0#. p2.6:5 i/o h(x) r(wl) i(x) p(x) port 2, pins 7:0 are multipurpose bidirectional port pins. they are multiplexed as follows: p2.7 with cts0#, p2.6 with txd0, p2.5 with rxd0, and p2.4:0 with cs4:0#. p3.7:0 i/o h(x) r(wl) i(x) p(x) port 3, pins 7:0 are multipurpose bidirectional port pins. they are multiplexed as follows: p3.7 with comclk, p3.6 with pwrdown, p3.5:2 with int3:0, and p3.1:0 with tmrout1:0 and int8:9. ta ble 4 . intel386? ex microprocessor pin descriptions (sheet 3 of 6) symbol type output states name and function notes: 1. x if clock source is internal; q if clock source is external 2. q if jtag unit is shifting out data, z if it is not
intel386? ex embedded microprocessor 16 datasheet pwrdown o h(q) r(wl) i(x) p(1) powerdown indicates that the processor is in powerdown mode. pwrdown is multiplexed with p3.6. rd# o h(1) r(1) i(1) p(1) read enable indicates that the current bus cycle is a read cycle. ready# i/o h(z) r(z) i(z) p(z) ready indicates that the current bus transaction has completed. an external device or an internal signal can drive ready#. internally, the chip-select wait-state logic can generate the ready signal and drive the ready# pin active. reset st reset suspends any operation in progress and places the processor into a known reset state. refresh# o h(1) r(1) i(q) p(x) refresh indicates that the current bus cycle is a refresh cycle. refresh# is multiplexed with cs6#. ri1:0# i ring indicator sio1 and sio0 indicate that the modem or data set has received a telephone ringing signal. ri1# is multiplexed with ssiorx, and ri0# is multiplexed with p1.4 and has a temporary weak pull-up resistor. rts1# o h(x) r(wl) i(x) p(x) request-to-send sio1 and sio0 indicate that corresponding asynchronous serial channel is ready to exchange data with the modem or data set. rts1# is multiplexed with ssiotx, and rts0# is multiplexed with p1.1. rts0# o h(x) r(wh) i(x) p(x) request-to-send sio1 and sio0 indicate that corresponding asynchronous serial channel is ready to exchange data with the modem or data set. rts1# is multiplexed with ssiotx, and rts0# is multiplexed with p1.1. rxd1:0 i receive data sio1 and sio0 accept serial data from the modem or data set to the corresponding asynchronous serial channel. rxd1 is multiplexed with drq1, and rxd0 is multiplexed with p2.5 and has a temporary weak pull-down resistor. smi# st system management interrupt invokes system management mode (smm). smi# is the highest priority external interrupt. it is latched on its falling edge and forces the cpu into smm upon completion of the current instruction. smi# is recognized on an instruction boundary and at each iteration for repeat string instructions. smi# cannot interrupt locked bus cycles or a currently executing smm. when the processor receives a second smi# while in smm, it latches the second smi# on the smi# falling edge. however, the processor must exit smm by executing a resume instruction (rsm) before it can service the second smi#. smi# has a permanent weak pull-up resistor. smiact# o h(1) r(1) i(x) p(x) system management interrupt active indicates that the processor is operating in system management mode (smm). it is asserted when the processor initiates an smm sequence and remains asserted (low) until the processor executes the resume instruction (rsm). table 4. intel386? ex microprocessor pin descriptions (sheet 4 of 6) symbol type output states name and function notes: 1. x if clock source is internal; q if clock source is external 2. q if jtag unit is shifting out data, z if it is not
intel386? ex embedded microprocessor datasheet 17 srxclk i/o h(q) r(wh) i(q) p(x)/p(q) note 1 ssio receive clock synchronizes data being accepted by the synchronous serial port. srxclk is multiplexed with dtr1#. ssiorx i ssio receive serial data accepts serial data (most-significant bit first) being sent to the synchronous serial port. ssiorx is multiplexed with ri1#. ssiotx o h(q) r(wl) i(q) p(x)/p(q) note 1 ssio transmit serial data sends serial data (most-significant bit first) from the synchronous serial port. ssiotx is multiplexed with rts1#. intel does not specify a data hold time for ssiotx. slower external devices may require additional hardware to properly interface the ssio unit. stxclk i/o h(q) r(wh) i(q) p(x)/p(q) note 1 ssio transmit clock synchronizes data being sent by the synchronous serial port. stxclk is multiplexed with dsr1. tck i tap (test access port) controller clock provides the clock input for the jtag logic. it has a permanent weak pull-up resistor. tdi i tap (test access port) controller data input is the serial input for test instructions and data. it has a permanent weak pull- up resistor. tdo o h(z)/h(q) note 2 r(z)/r(q) note 2 i(z)/i(q) note 2 p(z)/ p(q) note 2 tap (test access port) controller data output is the serial output for test instructions and data. tmrclk2:0 i timer/counter clock inputs can serve as external clock inputs for the corresponding timer/counters. (the timer/counters can also be clocked internally.) they are multiplexed as follows: tmrclk2 with pereq, tmrclk1 with int6, and tmrclk0 with int4. tmrclk2 has a temporary weak pull-down resistor. tmrgate2:0 i timer/counter gate inputs can control the corresponding timer/counters counting (enable, disable, or trigger, depending on the programmed mode). they are multiplexed as follows: tmrgate2 with busy#, tmrgate1 with int7, and tmrgate0 with int5. tmrgate2 has a temporary weak pull- up resistor. tmrout2 o h(q) r(wh) i(q) p(x)/p(q) note 1 timer/counter outputs provide the output of the corresponding timer/counter. the form of the output depends on the programmed mode. they are multiplexed as follows: tmrout2 with error#, tmrout1 with p3.1 and int8, and tmrout0 with p3.0 and int9. tmrout1:0 o h(q) r(wl) i(q) p(x)/p(q) note 1 timer/counter outputs provide the output of the corresponding timer/counter. the form of the output depends on the programmed mode. they are multiplexed as follows: tmrout2 with error#, tmrout1 with p3.1 and int8, and tmrout0 with p3.0 and int9. tms i tap (test access port) controller mode select controls the sequence of the tap controllers states. it has a permanent weak pull-up resistor. ta ble 4 . intel386? ex microprocessor pin descriptions (sheet 5 of 6) symbol type output states name and function notes: 1. x if clock source is internal; q if clock source is external 2. q if jtag unit is shifting out data, z if it is not
intel386? ex embedded microprocessor 18 datasheet trst# st tap (test access port) controller reset resets the tap controller at power-up and each time it is activated. it has a permanent weak pull-up resistor. txd1 o h(q) r(1) i(q) p(x)/p(q) note 1 transmit data sio1 and sio0 transmit serial data from the individual serial channels. txd1 is multiplexed with dack1#, and txd0 is multiplexed with p2.6. txd0 o h(q) r(wl) i(q) p(x)/p(q) note 1 transmit data sio1 and sio0 transmit serial data from the individual serial channels. txd1 is multiplexed with dack1#, and txd0 is multiplexed with p2.6. ucs# o h(1) r(0) i(q) p(x) upper chip-select is activated when the address of a memory or i/o bus cycle is within the address region programmed by the user. v cc p system power provides the nominal dc supply input. this pin is connected externally to a v cc board plane. v ss g system ground provides the 0 v connection from which all inputs and outputs are measured. this pin is connected externally to a ground board plane. wdtout o h(q) r(0) i(q) p(x) watchdog timer output indicates that the watchdog timer has expired. w/r# o h(z) r(0) i(1) p(1) write/read indicates whether the current bus cycle is a write cycle or a read cycle. when w/r# is high, the bus cycle is a write cycle; when w/r# is low, the bus cycle is a read cycle. wr# o h(1) r(1) i(1) p(1) write enable indicates that the current bus cycle is a write cycle. table 4. intel386? ex microprocessor pin descriptions (sheet 6 of 6) symbol type output states name and function notes: 1. x if clock source is internal; q if clock source is external 2. q if jtag unit is shifting out data, z if it is not
intel386? ex embedded microprocessor datasheet 19 4.0 functional description the intel386 ex microprocessor is a fully static, 32-bit processor optimized for embedded applications. it features low power and low voltage capabilities, integration of many commonly used dos-type peripherals, and a 32-bit programming architecture compatible with the large software base of intel386 processors. the following sections provide an overview of the integrated peripherals. 4.1 clock generation and power management unit the clock generation circuit includes a divide-by-two counter, a programmable divider for generating a prescaled clock (psclk), a divide-by-two counter for generating baud-rate clock inputs, and reset circuitry. the clk2 input provides the fundamental timing for the chip. it is divided by two internally to generate a 50% duty cycle phase1 (ph1) and phase 2 (ph2) for the core and integrated peripherals. for power management, separate clocks are routed to the core (ph1c/ph2c) and the peripheral modules (ph1p/ph2p). to help synchronize with external devices, the ph1p clock is provided on the clkout output pin. two power management modes are provided for flexible power-saving options. during idle mode, the clocks to the cpu core are frozen in a known state (ph1c low and ph2c high), while the clocks to the peripherals continue to toggle. in powerdown mode, the clocks to both core and peripherals are frozen in a known state (ph1c low and ph2c high). the bus interface unit will not honor any dma, dram refresh, or hold requests in powerdown mode because the clocks to the entire device are frozen. 4.2 chip-select unit the chip-select unit (csu) decodes bus cycle address and status information and enables the appropriate chip-selects. the individual chip-selects become valid in the same bus state as the address and become inactive when either a new address is selected or the current bus cycle is complete. the csu is divided into eight separate chip-select regions, each of which can enable one of the eight chip-select pins. each chip-select region can be mapped into memory or i/o space. a memory-mapped chip-select region can start on any 2 ( n +1) kbyte address location (where n = 0C15, depending upon the mask register). an i/o-mapped chip-select region can start on any 2 ( n +1) byte address location (where n = 0C15, depending upon the mask register). the size of the region is also dependent upon the mask used. 4.3 interrupt control unit the intel386 ex processors interrupt control unit (icu) contains two 8259a modules connected in a cascade mode. these modules are similar to the industry-standard 8259a architecture. the interrupt control unit directly supports up to ten external (int9:0) and up to eight internal interrupt request signals. pending interrupt requests are posted in the interrupt request registers, which contain one bit for each interrupt request signal. when an interrupt request is asserted, the corresponding interrupt request register bit is set. the 8259a modules can be programmed to
intel386? ex embedded microprocessor 20 datasheet recognize either an active-high level or a positive transition on the interrupt request lines. an internal priority resolver decides which pending interrupt request (if more than one exists) is the highest priority, based on the programmed operating mode. the priority resolver controls the single interrupt request line to the cpu. the priority resolvers default priority scheme places the master interrupt controllers ir0 as the highest priority and the masters ir7 as the lowest. the priority can be modified through software. besides the ten interrupt request inputs available to the intel386 ex microprocessor, additional interrupts can be supported by cascaded external 8259a modules. up to four external 8259a units can be cascaded to the master through connections to the int3:0 pins. in this configuration, the interrupt acknowledge (inta#) signal can be decoded externally using the ads#, d/c#, w/r#, and m/io# signals. 4.4 timer/counter unit the timer/counter unit (tcu) on the intel386 ex microprocessor has the same basic functionality as the industry-standard 82c54 counter/timer. the tcu provides three independent 16-bit counters, each capable of handling clock inputs up to 8 mhz. this maximum frequency must be considered when programming the input clocks for the counters. six programmable timer modes allow the counters to be used as event counters, elapsed-time indicators, programmable one- shots, and in many other applications. all modes are software programmable. 4.5 watchdog timer unit the watchdog timer (wdt) unit consists of a 32-bit down-counter that decrements every ph1p cycle, allowing up to 4.3 billion count intervals. the wdtout pin is driven high for sixteen clk2 cycles when the down-counter reaches zero (the wdt times out). the wdtout signal can be used to reset the chip, to request an interrupt, or to indicate to the user that a ready-hang situation has occurred. the down-counter can also be updated with a user-defined 32-bit reload value under certain conditions. alternatively, the wdt unit can be used as a bus monitor or as a general-purpose timer. 4.6 asynchronous serial i/o unit the intel386 ex microprocessors asynchronous serial i/o (sio) unit is a universal asynchronous receiver/ transmitter (uart). functionally, it is equivalent to the national semiconductor ns16450 and ins8250. the intel386 ex embedded processor contains two full- duplex, asynchronous serial channels. the sio unit converts serial data characters received from a peripheral device or modem to parallel data and converts parallel data characters received from the cpu to serial data. the cpu can read the status of the serial port at any time during its operation. the status information includes the type and condition of the transfer operations being performed and any errors (parity, framing, overrun, or break interrupt).
intel386? ex embedded microprocessor datasheet 21 each asynchronous serial channel includes full modem control support (cts#, rts#, dsr#, dtr#, ri#, and dcd#) and is completely programmable. the programmable options include character length (5, 6, 7, or 8 bits), stop bits (1, 1.5, or 2), and parity (even, odd, forced, or none). in addition, it contains a programmable baud-rate generator capable of clock rates from 0 to 512 kbaud. 4.7 synchronous serial i/o unit the synchronous serial i/o (ssio) unit provides for simultaneous, bidirectional communications. it consists of a transmit channel, a receive channel, and a dedicated baud-rate generator. the transmit and receive channels can be operated independently (with different clocks) to provide non-lockstep, full-duplex communications; either channel can originate the clocking signal (master mode) or receive an externally generated clocking signal (slave mode). the ssio provides numerous features for ease and flexibility of operation. with a maximum clock input of clk2/4 to the baud-rate generator, the ssio can deliver a baud rate of up to 8.25 mbits per second with a processor clock of 33 mhz. each channel is double buffered. the two channels share the baud-rate generator and a multiply-by-two transmit and receive clock. the ssio supports 16-bit serial communications with independently enabled transmit and receive functions and gated interrupt outputs to the interrupt controller. 4.8 parallel i/o unit the intel386 ex microprocessor has three 8-bit, general-purpose i/o ports. all port pins are bidirectional, with ttl-level inputs and cmos-level outputs. all pins have both a standard operating mode and a peripheral mode (a multiplexed function), and all have similar sets of control registers located in i/o address space. 4.9 dma and bus arbiter unit the intel386 ex microprocessors dma controller is a two-channel dma; each channel operates independently of the other. within the operation of the individual channels, several different data transfer modes are available. these modes can be combined in various configurations to provide a very versatile dma controller. its feature set has enhancements beyond the 8237 dma family; however, it can be configured such that it can be used in an 8237-like mode. each channel can transfer data between any combination of memory and i/o with any combination (8 or 16 bits) of data path widths. an internal temporary register that can disassemble or assemble data to or from either an aligned or a nonaligned destination or source optimizes bus bandwidth. the bus arbiter, a part of the dma controller, works much like the priority resolving circuitry of a dma. it receives service requests from the two dma channels, the external bus master, and the dram refresh control unit. the bus arbiter requests bus ownership from the core and resolves priority issues among all active requests when bus mastership is granted. each dma channel consists of three major components: the requestor, the target, and the byte count. these components are identified by the contents of programmable registers that define the memory or i/o device being serviced by the dma. the requestor is the device that requires and requests service from the dma controller. only the requestor is considered capable of initializing
intel386? ex embedded microprocessor 22 datasheet or terminating a dma process. the target is the device with which the requestor wishes to communicate. the dma process considers the target a slave that is incapable of controlling the process. the byte count dictates the amount of data that must be transferred. 4.10 refresh control unit the refresh control unit (rcu) simplifies dynamic memory controller design with its integrated address and clock counters. integrating the rcu into the processor allows an external dram controller to use chip-selects, wait state logic, and status lines. the refresh control unit: ? provides a programmable-interval timer ? provides the bus arbitration logic to gain control of the bus to run refresh cycles ? contains the logic to generate row addresses to refresh dram rows individually ? contains the logic to signal the start of a refresh cycle the rcu contains a 13-bit address counter that forms the refresh address, supporting drams with up to 13 rows of memory cells (13 refresh address bits). this includes all practical dram sizes for the intel386 ex microprocessor's 64 mbyte address space. 4.11 jtag test-logic unit the jtag test-logic unit provides access to the device pins and to a number of other testable areas on the device. it is fully compliant with the ieee 1149.1 standard and thus interfaces with five dedicated pins: trst#, tck, tms, tdi, and tdo. it contains the test access port (tap) finite- state machine, a 4-bit instruction register, a 32-bit identification register, and a single-bit bypass register. the test-logic unit also contains the necessary logic to generate clock and control signals for the boundary scan chain. since the test-logic unit has its own clock and reset signals, it can operate autonomously. while the rest of the microprocessor is in reset or powerdown, the jtag unit can read or write various register chains.
intel386? ex embedded microprocessor datasheet 23 5.0 design considerations this section describes the intel386 ex microprocessors instruction set and its component and revision identifiers. 5.1 instruction set the intel386 ex microprocessor uses the same instruction set as the intel386 sx microprocessor with the following exceptions. the intel386 ex microprocessor has one new instruction (rsm). this resume instruction causes the processor to exit system management mode (smm). rsm requires 338 clocks per instruction (cpi). the intel386 ex microprocessor requires more clock cycles than the intel386 sx microprocessor to execute some instructions. table 5 lists these instructions and the intel386 ex microprocessor clock count. for the equivalent intel386 sx microprocessor clock count, refer to the instruction set clock count summary table in the intel386? sx microprocessor datasheet (order number 240187). table 5. microprocessor clocks per instruction instruction clock count (1) virtual 8086 mode (2) real address mode or virtual 8086 mode protected virtual address mode (3) popa 29 35 in: fixed port variable port 27 28 14 15 8/29 9/29 out: fixed port variable port 27 28 14 15 8/29 9/29 ins 30 17 10/32 outs 31 18 11/33 rep ins 31+6 n (note 4 ) 17+7 n (note 4 ) 11+7 n /32+6 n (note 4 ) rep outs 30+8 n (note 4 ) 16+8 n (note 4 ) 10+8 n /31+8 n (note 4 ) hlt 7 7 mov cr0, reg 10 10 notes: 1. for in, out, ins, outs, rep ins, and rep outs instructions, add one clock count for each wait state generated by the peripheral being accessed (the values in the table are for zero wait state). 2. the clock count values in this column apply if i/o permission allows i/o to the port in virtual 8086 mode. if the i/o bit map denies permission, exception fault 13 occurs; see clock counts for the int 3 instruction in the instruction set clock count summary table in the intel386? sx microprocessor datasheet (order number 240187). 3. when two clock counts are listed, the smaller value refers to the case where cpl iopl and the larger value refers to the case where cpl>iopl. cpl is the current privilege level, and iopl is the i/o privilege level. 4. n = the number of times repeated.
intel386? ex embedded microprocessor 24 datasheet 5.2 component and revision identifiers to assist users, the microprocessor holds a component identifier and revision identifier in its dx register after reset. the upper 8 bits of dx hold the component identifier, 23h. (the lower nibble, 3h, identifies the intel386 architecture, while the upper nibble, 2h, identifies the second member of the intel386 microprocessor family.) the lower 8 bits of dx hold the revision level identifier. the revision identifier will, in general, chronologically track those component steppings that are intended to have certain improvements or distinction from previous steppings. the revision identifier will track that of the intel386 cpu whenever possible. however, the revision identifier value is not guaranteed to change with every stepping revision or to follow a completely uniform numerical sequence, depending on the type or intent of the revision or the manufacturing materials required to be changed. intel has sole discretion over these characteristics of the component. the initial revision identifier for the intel386 ex microprocessor is 09h. 5.3 package thermal specifications the intel386 ex microprocessor is specified for operation with a minimum case temperature (t case(min) ) of -40 c and a maximum case temperature (t case(max) ) dependent on power dissipation (see figures 4 through 7). the case temperature can be measured in any environment to determine whether the microprocessor is within the specified operating range. the case temperature should be measured at the center of the top surface opposite the pins. an increase in the ambient temperature (t a ) causes a proportional increase in the case temperature (t case ) and the junction temperature (t j ), which is the junction temperature on the die itself. a packaged device produces thermal resistance between junction and case temperatures ( q jc ) and between junction and ambient temperatures ( q ja ). the relationships between the temperature and thermal resistance parameters are expressed by these equations: t j = t case + p q jc t a = t j C p q ja t case = t a + p [ q ja C q jc ] p = power dissipated as heat = v cc i cc a safe operating temperature can be calculated from the above equations by using the maximum safe t j of 120 c, the power drawn by the chip in the specific design, and the q jc value from table 6. the q ja value depends on the airflow (measured at the top of the chip) provided by the system ventilation, board layout, board thickness, and potentially other factors in the design of the application. the q ja values are given for reference only and are not guaranteed. figures 4 through 7 provide maximum case temperature as a function of frequency. table 6. thermal resistances (0c/w) q ja , q jc package q jc q ja vs. airflow (ft/min) 0100200 132 pqfp 7 28 24 22 144 tqfp 4 36 31 27
intel386? ex embedded microprocessor datasheet 25 figure 4. maximum case temperature vs. frequency for typical power values (132-lead pqfp, v cc = 5.5 v) figure 5. maximum case temperature vs. frequency for typical power values (144-lead tqfp, v cc = 5.5 v nominal) a3346-02 107 16 20 25 113.9 112.25 110.7 132 lead pqfp tc (deg c) operating frequency (mhz) 108 109 110 111 112 113 114 33 107.8 a3347-02 108 16 20 25 114.9 113.5 112.25 144 lead tqfp tc (deg c) operating frequency (mhz) 109 110 111 112 113 114 115 116 33 109.8
intel386? ex embedded microprocessor 26 datasheet figure 6. maximum case temperature vs. frequency for typical power values (132-lead pqfp, v cc = 3.6 v) figure 7. maximum case temperature vs. frequency for typical power values (144-lead tqfp, v cc = 3.6 v) a3348-02 117.5 117.0 116.5 16 20 25 117.5 117.0 116.5 132 lead pqfp tc (deg c) operating frequency (mhz) a3349-01 118.0 117.5 117.0 16 20 25 118.0 117.5 117.0 144 lead tqfp tc (deg c) operating frequency (mhz)
intel386? ex embedded microprocessor datasheet 27 6.0 electrical specifications 6.1 maximum ratings warning: stressing the device beyond the maximum ratings may cause permanent damage. these are stress ratings only. table 7. 5 v intel386 extc processor maximum ratings parameter maximum rating storage temperature C65c to +150c supply voltage with respect to v ss C0.5 v to 6.5 v voltage on other pins C0.5 v to v cc + 0.5 v v cc (digital supply voltage) 4.5 v to 5.5 v t case (case temperature under bias) t case(min) t case(max) -40c (see figures 4 and 5) f osc (operating frequency) 0 mhz to 33 mhz table 8. 3 v intel386 extb processor maximum ratings parameter maximum rating storage temperature C65c to +150c supply voltage with respect to v ss C0.5 v to 4.6 v voltage on other pins C0.5 v to v cc + 0.5 v v cc (digital supply voltage) 20 mhz 2.7 v to 3.6 v 25 mhz 3.0 v to 3.6 v t case (case temperature under bias) t case(min) t case(max) -40c (see figures 6 and 7) f osc (operating frequency) 0 mhz to 25 mhz
intel386? ex embedded microprocessor 28 datasheet 6.2 dc specifications table 9. 5-volt dc characteristics symbol parameter min. max. unit test condition v il input low voltage for all input pins except clk2, trst#, reset, smi#, and nmi C0.3 0.8 v v ih input high voltage for all input pins except clk2, trst#, reset, smi#, and nmi 2.0 v cc + 0.3 v v ilc input low voltage for clk2, trst#, reset, smi#, and nmi -0.3 0.8 v v ihc input high voltage for clk2, trst#, reset, smi#, and nmi v cc -0.8 v cc +0.3 v v ol output low voltage all pins except port 3 port 3 0.45 0.45 v v i ol = 8 ma i ol = 16 ma v oh output high voltage all output pins all pins except port 3 port 3 pins (2 max) v cc -0.5 2.45 2.45 v v v i oh = C0.2 ma i oh = C8 ma i oh = C16 ma v olc clkout 0.45 v i ol = 2 ma v ohc clkout v cc -0.5 2.45 v i oh = C0.2 ma i oh = C2 ma i li input leakage current 15 a 0 v in v cc flt# is not tested for i li i lo output leakage current 15 a 0.45v v out v cc i cc supply current 320 250 ma ma f osc =33 mhz f osc =25 mhz (tested with device held in reset, inputs held in their inactive state) i idle idle mode current 110 85 ma ma f osc =33 mhz f osc =25 mhz i pd powerdown current 100 a c s pin capacitance (any pin to v ss ) 10 pf not tested
intel386? ex embedded microprocessor datasheet 29 table 10. 3-volt dc characteristics symbol parameter min. max. unit test condition v il input low voltage for all input pins except clk2, trst#, reset, smi#, and nmi C0.3 0.8 v v ih input high voltage for all input pins except clk2, trst#, reset, smi#, and nmi 2.0 v cc + 0.3 v v ilc input low voltage for clk2, trst#, reset, smi#, and nmi -0.3 0.8 v v ihc input high voltage for clk2, trst#, reset, smi#, and nmi v cc -0.6 v cc +0.3 v v ol output low voltage all pins except port 3 port 3 pins (2 max) 0.20 0.45 0.45 v v v i ol = 100 a, 2.7 v v cc 3.6 v (lvcmos) i ol = 4ma, 3.0 v v cc 3.6 v (lvttl) i ol = 8ma, 3.0 v v cc 3.6 v (lvttl) v oh output high voltage all pins except port 3 port 3 v cc -0.2 v cc -0.65 v cc -0.65 v v v i oh = -100 a, 2.7 v v cc 3.6 v (lvcmos) i oh = -4ma, 3.0 v v cc 3.6v (lvttl) i oh = -8ma, 3.0 v v cc 3.6v (lvttl) v olc clkout 0.2 0.45 v i ol = 100 a, 2.7 v v cc 3.6 v i ol = 1 ma, 3.0 v v cc 3.6 v (lvttl) v ohc clkout v cc -0.2 v cc -0.65 v i oh = -100 a, 2.7 v v cc 3.6 v i oh = -1 ma, 3.0 v v cc 3.6 v (lvttl) i li input leakage current 5 a 0 v in v cc flt# is not tested for i li i lo output leakage current 15 a 0.45v v out v cc i cc supply current 140 110 ma ma f osc = 25 mhz, v cc =3.6 v f osc = 20 mhz, v cc =3.6 v (tested with device held in reset, inputs held in their inactive state) i idle idle mode current 50 40 ma ma f osc = 25 mhz, v cc =3.6 v f osc = 20 mhz, v cc =3.6 v i pd powerdown current 100 a c s pin capacitance (any pin to v ss ) 10 pf not tested
intel386? ex embedded microprocessor 30 datasheet 6.3 ac specifications table 11 lists output delays, input setup requirements, and input hold requirements for the 5 v extc processor; table 12 is for the extb processor. all ac specifications are relative to the clk2 rising edge crossing the v cc /2 level for the extb, or 2.0 volts for the extc. figures 8 and 9 show the measurement points for ac specifications for the extb and extc processors. inputs must be driven to the indicated voltage levels when ac specifications are measured. output delays are specified with minimum and maximum limits measured as shown. the minimum delay times are hold times provided to external circuitry. input setup and hold times are specified as minimums, defining the smallest acceptable sampling window. within the sampling window, a synchronous input signal must be stable for correct operation. outputs ads#, w/r#, cs5:0#, ucs#, d/c#, m/io#, lock#, bhe#, ble#, refresh#/cs6#, ready#, lba#, a25:1, hlda and smiact# change only at the beginning of phase one. d15:0 (write cycles) and pwrdown change only at the beginning of phase two. rd# and wr# change to their active states at the beginning of phase two. rd# changes to its inactive state (end of cycle) at the beginning of phase one. see the intel386? ex embedded microprocessor user's manual for a detailed explanation of early ready# vs. late ready#. the ready#, hold, busy#, error#, pereq, bs8#, and d15:0 (read cycles) inputs are sampled at the beginning of phase one. the na#, smi#, and nmi inputs are sampled at the beginning of phase two. figure 8. drive levels and measurement points for ac specifications (extc) a b tx valid output n+1 a a c c b min max c d clk2 outputs (a25:1,bhe# ble#,ads#,m/io# d/c#w/r#,lock# hlda, smiact#) outputs (d15:0) inputs (n/a#,intr nmi,smi#) inputs (ready#,hold flt#,error# busy#,pereq d15:0,a20) legend a - v cc /2 b - 2.0v c = 1.5v a - maximum output delay spec b - minimum output delay spec c - minimum input setup spec d - minimum input hold spec ph1 ph2 3.0v 0v valid output n a b valid output n+1 a a min max valid output n valid input c c c d 3.0v 0v valid input
intel386? ex embedded microprocessor datasheet 31 figure 9. drive levels and measurement points for ac specifications (extb) a b tx valid output n+1 a a b b a min max c d clk2 outputs (a25:1,bhe# ble#,ads#,m/io# d/c#w/r#,lock# hlda, smiact#) outputs (d15:0) inputs (n/a#,intr nmi,smi#) inputs (ready#,hold flt#,error# busy#,pereq d15:0,a20) legend a - v cc /2 b = 1.5v a - maximum output delay spec b - minimum output delay spec c - minimum input setup spec d - minimum input hold spec ph1 ph2 2.0v 0v valid output n a b valid output n+1 a a min max valid output n valid input b b c d 2.0v 0v valid input a2600-02
intel386? ex embedded microprocessor 32 datasheet table 11. 5-volt ac characteristics (sheet 1 of 5) symbol parameter 33 mhz 25 mhz test condition min. (ns) max. (ns) min. (ns) max. (ns) operating frequency 0 33 0 25 one-half clk2 frequency in mhz (1) t 1 clk2 period 15 20 t 2a clk2 high time 6.25 7 (2) t 2b clk2 high time 4 4 (2) t 3a clk2 low time 6.25 7 (2) t 3b clk2 low time 4.5 5 (2) t 4 clk2 fall time 4 7 (2) t 5 clk2 rise time 4 7 (2) t 6 a25:1 valid delay 4 21 4 24 c l = 50 pf t 7 a25:1 float delay 4 28 4 28 (3) t 8 bhe#, ble#, lock# valid delay 4 21 4 24 c l = 50 pf t 8a smiact# valid delay 4 21 4 24 c l = 50 pf t 9 bhe#, ble#, lock# float delay 4 28 4 28 (3) t 10 m/io#, d/c#, w/r#, ads#, refresh# valid delay 421424c l = 50 pf t 10a rd#, wr# valid delay 4 18 4 22 t 10b wr# valid delay for the rising edge with respect to phase two (external late ready#) 4 28 4 28 (6) t 11 m/io#, d/c#, w/r#, refresh#, ads# float delay 4 28 4 28 (3) t 12 d15:0 write data valid delay 4 23 4 23 c l = 50 pf t 13 d15:0 write data float delay 4 22 4 22 (3) t 14 hlda valid delay 4 18 4 22 c l = 50 pf t 15 na# setup time 5 5 t 16 na# hold time 3 3 t 19 ready# setup time 8 9 t 19a bs8# setup time 11 11 note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor datasheet 33 t 20 ready#, bs8# hold time 4 4 t 21 d15:0 read setup time 7 7 t 22 d15:0 read hold time 4 4 t 23 hold setup time 8 8 t 24 hold hold time 3 3 t 25 reset setup time 5 5 t 26 reset hold time 2 3 t 27 nmi setup time 6 6 (4) t 27a smi# setup time 6 6 (4) t 28 nmi hold time 6 6 (4) t 28a smi# hold time 6 6 (4) t 29 pereq, error#, busy# setup time 6 6 (4) t 30 pereq, error#, busy# hold time 5 5 (4) t 31 ready# valid delay 4 24 4 26 c l = 30 pf t 32 ready# float delay 4 34 4 34 t 33 lba# valid delay 4 20 4 22 t 34 cs6:0#, ucs# valid delay 4 24 (25 in smm) 430c l = 30 pf t 35 clkout valid delay 2 9 2 14 c l = 30 pf t 36 pwrdown valid delay 4 15 4 18 t 41 a25:1, bhe#, ble# valid to wr# low 00 t 41a ucs#, cs6:0# valid to wr# low 0 0 t 42 a25:1, bhe#, ble# hold after wr# high 0 0 (6) t 42a ucs#, cs6:0# hold after wr# high 00 t 42b a25:1. bhe#, ble# hold after wr# high 10 10 (7, 8) table 11. 5-volt ac characteristics (sheet 2 of 5) symbol parameter 33 mhz 25 mhz test condition min. (ns) max. (ns) min. (ns) max. (ns) note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor 34 datasheet t 43 d15:0 output valid to wr# high 2clk2 C10 2clk2 C 10 (5) t 44 d15:0 output hold after wr# high clk2 C10 clk2 C10 t 45 wr# high to d15:0 float clk2 + 10 clk2 + 10 (3) t 46 wr# pulse width 2clk2 C10 2clk2 C10 (7) t 47 a25:1, bhe#, ble# valid to d15:0 va li d 4clk2 - 28 4clk2- 31 (5) t 47a ucs#, cs6:0# valid to d15-d0 va li d 4clk2 - 31 4clk2 - 35 (5) t 48 rd# low to d15:0 input valid 3clk2 C 25 3clk2 C 29 (5) t 49 d15:0 hold after rd# high 0 0 t 50 rd# high to d15:0 float clk2 clk2 (3) t 51 a25:1, bhe#, ble# hold after rd# high 00 t 51a ucs#, cs6:0# hold after rd# high 00 t 52 rd# pulse width 3clk2 C10 3clk2 C10 synchronous serial i/o (ssio) unit t 100 stxclk, srxclk frequency (master mode) clk2/8 clk2/8 (unit is mhz) t 101 stxclk, srxclk frequency (slave mode) clk2/8 clk2/8 (unit is mhz) t 102 stxclk, srxclk low time 7clk2/2 7clk2/2 (2) t 103 stxclk, srxclk high time 7clk2/2 7clk2/2 (2) t 104 stxclk low to ssiotx delay 3clk2 3clk2 t 105 ssiorx to srxclk high setup time 0 0 (2) t 106 ssiorx from srxclk hold time 3clk2 3clk2 table 11. 5-volt ac characteristics (sheet 3 of 5) symbol parameter 33 mhz 25 mhz test condition min. (ns) max. (ns) min. (ns) max. (ns) note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor datasheet 35 timer control unit (tcu) inputs t 107 tmrclk n frequency 8 8 (unit is mhz) t 108 tmrclk n low 60 60 t 109 tmrclk n high 60 60 t 11 0 tmrgate n high width 50 50 t 111 tmrgate n low width 50 50 t 11 2 tmrgate n to tmrclk setup time (external tmrclk only) 10 10 t 112a tmrgate n to tmrclk hold time (external tmrclk only) 11 11 timer control unit (tcu) outputs t 11 3 tmrgate n low to tmrout valid 29 32 t 11 4 tmrclk n low to tmrout valid 29 32 interrupt control unit (icu) inputs t 11 5 d7:0 setup time (inta# cycle 2) 77 t 11 6 d7:0 hold time (inta# cycle 2) 44 interrupt control unit (icu) outputs t 11 7 clk2 high to cas2:0 valid 25 28 dma unit inputs t 11 8 dreq setup time (sync mode) 15 15 t 11 9 dreq hold time (sync mode) 4 4 (2) t 120 dreq setup time (async mode) 99 t 121 dreq hold time (async mode) 9 9 (2) table 11. 5-volt ac characteristics (sheet 4 of 5) symbol parameter 33 mhz 25 mhz test condition min. (ns) max. (ns) min. (ns) max. (ns) note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor 36 datasheet t 122 eop# setup time (sync mode) 15 15 t 123 eop# hold time (sync mode) 44 t 124 eop# setup time (async mode) 99 t 125 eop# hold time (async mode) 99 dma unit outputs t 126 dack# output valid delay 4 21 4 25 t 127 eop# active delay 4 25 4 25 t 128 eop# float delay 4 25 4 25 (3) jtag test-logic unit t 129 tck frequency 10 10 (unit is mhz) table 11. 5-volt ac characteristics (sheet 5 of 5) symbol parameter 33 mhz 25 mhz test condition min. (ns) max. (ns) min. (ns) max. (ns) note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor datasheet 37 table 12. 3-volt ac characteristics (sheet 1 of 5) symbol parameter 25 mhz 3.0 v to 3.6 v 20 mhz 2.7 v to 3.6 v test condition min. (ns) max. (ns) min. (ns) max. (ns) operating frequency 0 25 0 20 one-half clk2 frequency in mhz (1) t 1 clk2 period 20 25 t 2a clk2 high time 7 8 (2) t 2b clk2 high time 4 5 (2) t 3a clk2 low time 7 8 (2) t 3b clk2 low time 5 6 (2) t 4 clk2 fall time 7 8 (2) t 5 clk2 rise time 7 8 (2) t 6 a25:1 valid delay 4 32 4 36 c l = 50 pf t 7 a25:1 float delay 4 29 4 36 (3) t 8 bhe#, ble#, lock# valid delay 432434c l = 50 pf t 8a smiact# valid delay 4 32 4 34 c l = 50 pf t 9 bhe#, ble#, lock# float delay 423432(3) t 10 m/io#, d/c#, w/r#, ads#, refresh# valid delay 432434c l = 50 pf t 10a rd#, wr# valid delay 4 30 4 32 t 10b wr# valid delay for the rising edge with respect to phase two (external late ready#) 437437(6) t 11 m/io#, d/c#, w/r#, refresh#, ads# float delay 430434(3) t 12 d15:0 write data valid delay 4 31 4 34 c l = 50 pf t 13 d15:0 write data float delay 4 20 4 28 (3) t 14 hlda valid delay 4 30 4 32 c l = 50 pf t 15 na# setup time 9 9 t 16 na# hold time 12 15 note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor 38 datasheet t 19 ready# setup time 15 17 t 19a bs8# setup time 17 19 t 20 ready#, bs8# hold time 4 4 t 21 d15:0 read setup time 9 11 t 22 d15:0 read hold time 6 6 t 23 hold setup time 17 22 t 24 hold hold time 5 5 t 25 reset setup time 12 13 t 26 reset hold time 4 4 t 27 nmi setup time 16 16 (4) t 27a smi# setup time 16 16 (4) t 28 nmi hold time 16 16 (4) t 28a smi# hold time 16 16 (4) t 29 pereq, error#, busy# setup time 14 16 (4) t 30 pereq, error#, busy# hold time 5 5 (4) t 31 ready# valid delay 4 33 4 42 c l = 30 pf t 32 ready# float delay 4 33 4 42 t 33 lba# valid delay 4 31 4 40 t 34 cs6:0#, ucs# valid delay 4 33 (34 in smm) 442c l = 30 pf t 35 clkout valid delay 4 14 4 18 c l = 30 pf t 36 pwrdown valid delay 4 26 4 29 t 41 a25:1, bhe#, ble# valid to wr# low 00 t 41a ucs#, cs6:0# valid to wr# low 00 t 42 a25:1, bhe#, ble# hold after wr# high 0 0 (6) table 12. 3-volt ac characteristics (sheet 2 of 5) symbol parameter 25 mhz 3.0 v to 3.6 v 20 mhz 2.7 v to 3.6 v test condition min. (ns) max. (ns) min. (ns) max. (ns) note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor datasheet 39 t 42a ucs#, cs6:0# hold after wr# high 00 t 42b a25:1. bhe#, ble# hold after wr# high 10 10 (7, 8) t 43 d15:0 output valid to wr# high 2clk2 C 10 2clk2 C 10 (5) t 44 d15:0 output hold after wr# high clk2 C10 clk2 C10 t 45 wr# high to d15:0 float clk2 + 10 clk2 +10 (3) t 46 wr# pulse width 2clk2 C10 2clk2 C10 (7) t 47 a25:1, bhe#, ble# valid to d15:0 valid 4clk2- 41 4clk2 - 45 (5) t 47a ucs#, cs6:0# valid to d15- d0 valid 4clk2 - 42 4clk2 - 53 (5) t 48 rd# low to d15:0 input valid 3clk2 C 39 3clk2 C 43 (5) t 49 d15:0 hold after rd# high 0 0 t 50 rd# high to d15:0 float clk2 clk2 (3) t 51 a25:1, bhe#, ble# hold after rd# high 00 t 51a ucs#, cs6:0# hold after rd# high 00 t 52 rd# pulse width 3clk2 C13 3clk2 C15 synchronous serial i/o (ssio) unit t 100 stxclk, srxclk frequency (master mode) clk2/8 clk2/8 (unit is mhz) t 101 stxclk, srxclk frequency (slave mode) clk2/8 clk2/8 (unit is mhz) t 102 stxclk, srxclk low time 7clk2/ 2 7clk2/ 2 (2) table 12. 3-volt ac characteristics (sheet 3 of 5) symbol parameter 25 mhz 3.0 v to 3.6 v 20 mhz 2.7 v to 3.6 v test condition min. (ns) max. (ns) min. (ns) max. (ns) note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor 40 datasheet t 103 stxclk, srxclk high time 7clk2/ 2 7clk2/ 2 (2) t 104 stxclk low to ssiotx delay 3clk2 3clk2 t 105 ssiorx to srxclk high setup time 0 0 (2) t 106 ssiorx from srxclk hold time 3clk2 3clk2 timer control unit (tcu) inputs t 107 tmrclk n frequency 8 8 (unit is mhz) t 108 tmrclk n low 60 60 t 109 tmrclk n high 60 60 t 11 0 tmrgate n high width 50 50 t 111 tmrgate n low width 50 50 t 11 2 tmrgate n to tmrclk setup time (external tmrclk only) 10 15 t 112a tmrgate n to tmrclk hold time (external tmrclk only) 19 19 timer control unit (tcu) outputs t 11 3 tmrgate n low to tmrout va li d 44 52 t 11 4 tmrclk n low to tmrout va li d 48 52 table 12. 3-volt ac characteristics (sheet 4 of 5) symbol parameter 25 mhz 3.0 v to 3.6 v 20 mhz 2.7 v to 3.6 v test condition min. (ns) max. (ns) min. (ns) max. (ns) note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor datasheet 41 interrupt control unit (icu) inputs t 115 d7:0 setup time (inta# cycle 2) 911 t 116 d7:0 hold time (inta# cycle 2) 66 interrupt control unit (icu) outputs t 117 clk2 high to cas2:0 valid 36 46 dma unit inputs t 118 dreq setup time (sync mode) 19 21 t 119 dreq hold time (sync mode) 4 4 (2) t 120 dreq setup time (async mode) 11 11 t 121 dreq hold time (async mode) 11 11 (2) t 122 eop# setup time (sync mode) 17 21 t 123 eop# hold time (sync mode) 44 t 124 eop# setup time (async mode) 11 11 t 125 eop# hold time (async mode) 11 11 dma unit outputs t 126 dack# output valid delay 4 31 4 33 t 127 eop# active delay 4 27 4 33 t 128 eop# float delay 4 27 4 33 (3) jtag test-logic unit t 129 tck frequency 10 10 (unit is mhz) table 12. 3-volt ac characteristics (sheet 5 of 5) symbol parameter 25 mhz 3.0 v to 3.6 v 20 mhz 2.7 v to 3.6 v test condition min. (ns) max. (ns) min. (ns) max. (ns) note: 1. tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies. 2. these are not tested. they are guaranteed by characterization. 3. float condition occurs when maximum output current becomes less than i lo in magnitude. float delay is not fully tested. 4. these inputs may be asynchronous to clk2. the setup and hold specifications are given to ensure recognition within a specific clk2 period. 5. these specifications are for information only and are not tested. they are intended to assist the designer in selecting memory speeds. for each wait state in the design add two clk2 cycles to the specification. 6. this specification assumes that ready# goes active after the rising edge of phase 2, so that wr# goes inactive as a result of ready# falling. 7. this specification assumes that ready# goes active before the rising edge of phase 2, so that wr# goes inactive as a result of phase 2 rising. 8. this specification applies if ready# is generated internally.
intel386? ex embedded microprocessor 42 datasheet figure 10. ac test loads figure 11. clk2 waveform cpu output c l clk2 t 4 a b c a = vcc ? 0.8 for vcc = 4.5 ? 5.5, vcc ? 0.6 for vcc = 2.7 ? 3.6 b = vcc/2 c = 0.8v t 3b t 3a t 1 t 2a t 2b t 5
intel386? ex embedded microprocessor datasheet 43 figure 12. ac timing waveforms input setup and hold timing a2736-01 clk2 tx tx tx ready# (input) bs8# dreq eop# (input) hold d15:0 (input) busy# error# pereq na# nmi smi# ph2 ph1 ph2 ph1 t 19 t 20 t 23 t 24 t 21 t 22 t 29 t 30 t 15 t 16 t 27 t 28 t 27a t 28a t 19a, t 118, t 120 t 122, t 124 t 119, t 121 t 123, t 125 t 115 t 116
intel386? ex embedded microprocessor 44 datasheet figure 13. ac timing waveforms output valid delay timing figure 14. ac timing waveforms output valid delay timing for external late ready# clk2 tx tx tx bhe#, ble# lock#, smiact# w/r#, m/io#, d/c# ads#,refresh# lba#, dack# eop# (output) ready# (output) a25:1, cs6:0#,ucs#, rd# inactive d15:0, cas2:0 rd#, wr# active, wr# inactive (early ready#) ph2 ph1 ph2 ph1 min valid n+1 valid n max min valid n+1 valid n max min valid n+1 valid n max min valid n+1 max valid n hlda t 8, t 8a t 10, t 31, t 33 t 126, t 127 t 10a, t 6, t 34 t 117, t 10a , t 12 a2737-01 clk2 ads# external ready# wr# t1 t2 t1 a4398-01 t10b
intel386? ex embedded microprocessor datasheet 45 figure 15. ac timing waveforms output float delay and hlda valid delay timing figure 16. ac timing waveforms reset setup and hold timing and internal phase clk2 ti or t1 bhe#, ble# lock# w/r#, m/io# d/c#, ads# refresh# ready# (output) a25:1 d15:0 ph2 ph1 ph2 ph1 min max hlda ph2 th min max (high z) min max min max (high z) min max min max (high z) min max min max (high z) t 13 also applies to data float when write cycle is followed by read or idle. min max min max t 8 t 10 t 6 t 32, t 11 t 7 t 9 t 13 t 14 t 14 t 12 a2738-01 clk2 reset ph2 ph1 ph2 or ph1 ph2 or ph1 reset initialization sequence t 26 t 25
intel386? ex embedded microprocessor 46 datasheet figure 17. ac timing waveforms relative signal timing figure 18. ac timing waveforms ssio timing figure 19. ac timing waveforms timer/counter timing a2705-01 d15:0 (in) wr# a25:1, ble#, bhe# ph2 clk2 t47 t47a t49 t42a t46 t1 t2 ti ucs#, cs6:0# d15:0 (out) rd# t52 t41 t41a t42 t43 t45 t44 t51a t51 t48 t50 a2712-01 ssiorx t104 stxclk t102 t100, t101 t103 t105 t106 ssiotx srxclk t102 t100, t101 t103 valid tx data valid rx data tmrout t113 tmrclk t109 t107 t108 tmrgate t111 t110 t114 t112a t112
intel386? ex embedded microprocessor datasheet 47 7.0 bus cycle waveforms figures 20 through 30 present various bus cycles that are generated by the processor. what is shown in the figure is the relationship of the various bus signals to clk2. these figures along with the information present in ac specifications allow the user to determine critical timing analysis for a given application. figure 20. basic internal and external bus cycles state a25:1, bhe# ble#, d/c# m/io# w/r# ads# na# d15:0 rd# wr# bs8# lock# t1 t2 t1 t2 t1 t2 ti t1 t2 cycle 1 nonpipelined external (write) [late ready] cycle 2 nonpipelined internal (read) cycle 3 nonpipelined internal (write) [early ready] cycle 4 nonpipelined external (read) refresh# lba# clk2 clkout valid 1 valid 2 valid 3 out 1 valid 1 valid 2 valid 3 in 2 out 3 in 4 idle cycle idle cycle idle cycle ti ti end cycle 1 end cycle 2 end cycle 3 ready# end cycle 4 valid 4 valid 4 a2486-03
intel386? ex embedded microprocessor 48 datasheet figure 21. nonpipelined address read cycles a2487-03 lock# d15:0 clk2 bhe#, ble#, a25:1 m/io#, d/c# valid1 rd# ready# ti t1 t2 t1 t2 t2 ti cycle 1 non-pipelined external (read) cycle 2 non-pipelined external (read) idle clkout idle ads# na# refresh# w/r# end cycle end cycle in1 in2 wr# lba# bs8# valid2 valid1 valid2
intel386? ex embedded microprocessor datasheet 49 figure 22. pipelined address cycle a2477-03 lock# d15:0 valid 2 valid 3 valid 4 clk2 bhe#, ble#, a25:1, m/io#, d/c# valid3 valid4 valid2 valid1 w/r# ads# na# t1p t2p t2p t1p t2 t2p t1p t2i t2p t1p cycle 1 pipelined (write) [late ready] cycle 2 non-pipelined (read) cycle 3 pipelined (write) [late ready] cycle 4 pipelined (read) clkout ads# is asserted as soon as the cpu has another bus cycle to perform, which is not always immediately after na# is asserted. as long as the cpu enters the t2p state during cycle 3, address pipelining is maintained in cycle 4. note ads# is asserted in every t2p state. in 2 asserting na# more than once during any cycle has no additional effects na# could have been asserted in t1p if desired. assertion now is the latest time possible to allow the cpu to enter t2p state to maintain pipelining in cycle 3. ready# rd# wr# lba# bs8# out 1 out valid 1 out 3 t2
intel386? ex embedded microprocessor 50 datasheet figure 23. 16-bit cycles to 8-bit devices (using bs8#) state a25:1 m/io# d/c# w/r# bhe# ads# na# d15:8 rd# wr# bs8# ready# lock# low byte write [late ready] high byte write [late ready] low byte read high byte read t1 t2 t1 t2 t1 t2 t1 t2 ti idle cycles ti ble# d7:0 must be high clk2 clkout a3375-01 data out high data out low data out high data in high data in low valid 1 valid 2 valid 1 valid 2
intel386? ex embedded microprocessor datasheet 51 figure 24. basic external bus cycles state a25:1, bhe# ble#, d/c# m/io# w/r# ads# na# d15:0 rd# wr# bs8# ready# lock# t1 t2 t1 t2 ti t1 t2 t1 t2 a2305-02 cycle 1 nonpipelined external (write) [late ready] cycle 2 nonpipelined external (read) cycle 3 nonpipelined external (write) [late ready] cycle 4 nonpipelined external (read) idle cycle refresh# lba# clk2 clkout valid 1 valid 2 valid 3 out 1 in 2 out 3 in 4 valid 1 valid 2 valid 3 valid 4 valid 4
intel386? ex embedded microprocessor 52 datasheet figure 25. nonpipelined address write cycles a2488-02 lock# d15:0 clk2 bhe#, ble#, a25:1 m/io#, d/c# rd# ready# ti t1 t2 t1 t2 t2 ti cycle 1 nonpipelined external (write) [late ready] cycle 2 nonpipelined external (write) [early ready] idle clkout idle ads# na# refresh# w/r# end cycle 1 end cycle 2 wr# lba# valid 2 valid 1 bs8# valid2 valid1 out 2 out 1
intel386? ex embedded microprocessor datasheet 53 figure 26. halt cycle a2492-02 lock# d15:0 clk2 bhe#, a1, m/io#, w/r# rd# ready# t1 t2 t1 t2 ti ti ti ti cycle 1 nonpipelined (write) [late ready] clkout cycle 2 nonpipelined (halt) ads# na# a25:2, ble#, d/c# wr# lba# idle float valid 1 cpu remains halted until intr, smi#, nmi, or reset is asserted. cpu responds to hold input while in the halt state. halt cycle must be acknowledged by ready# asserted. this ready# could be generated internally or externally. valid 2 ? ? out undefined valid 1 valid 1
intel386? ex embedded microprocessor 54 datasheet figure 27. basic refresh cycle a2491-02 lock# d15:0 clk2 ucs#, cs6:0#, bhe#, ble# m/io#, d/c# valid 1 rd# ready# ti t1 t2 ti t1 t2 t2 ti ti t1 cycle 1 nonpipelined external (read) cycle 2 refresh clkout idle idle cycle 3 nonpipelined external (write) [late ready] t2 valid 3 ads# na# a25:1 w/r# wr# lba# idle refresh# float hold hlda in out valid 1 valid 2 valid 1 valid 2 valid 3
intel386? ex embedded microprocessor datasheet 55 figure 28. refresh cycle during hold/hlda a2493-02 d15:0 hold clk2 bhe#, ble# m/io#, d/c# floating floating rd# ready# ti th th th ti t1 t2 ti ti th hold acknowledge cycle 1 refresh clkout idle idle idle th ads# na# refresh# w/r# wr# lba# lock# hold acknowledge a25:1 hlda floating due to refresh pending. floating floating floating floating floating floating floating floating floating floating valid 1
intel386? ex embedded microprocessor 56 datasheet figure 29. lock# signal during address pipelining figure 30. interrupt acknowledge cycles a2489-02 lock# clkout unlocked bus cycle locked bus cycle locked bus cycle ble#, bhe#, a25:1 unlocked bus cycle lock deasserted address asserted ready# a2490-03 clk2 bhe# ble#, a25:19, cas2:0,a15:3, a1 m/io#, d/c#, w/r# lba# lock# t2 t1 t2 ti ti ti ti t1 t2 ti interrupt acknowledge cycle 1 (internal) idle (four bus states) idle clkout rd# a2 ti previous cycle interrupt acknowledge cycle 2 (internal) ads# ready# wr#

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